Equalization for transmitter input buffer array

ABSTRACT

The present invention relates to data communication techniques and integrated circuit devices. More specifically, embodiments of the present invention provide an input buffer module that utilizes one or more equalization elements. The input buffer module includes an array of inverters arranged in a series. An equalization element is configured in series relative to a segment of the array of inverters. The resistance value of the equalization element is predetermined based on a delay associated with the segment of the array of inverters. There are other embodiments as well.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application is a continuation of and claims priority to U.S.application Ser. No. 15/699,882, filed Sep. 8, 2017, commonly assignedand incorporated by reference herein for all purposes.

STATEMENT AS TO RIGHTS TO INVENTIONS MADE UNDER FEDERALLY SPONSOREDRESEARCH AND DEVELOPMENT

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REFERENCE TO A “SEQUENCE LISTING,” A TABLE, OR A COMPUTER PROGRAMLISTING APPENDIX SUBMITTED ON A COMPACT DISK

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BACKGROUND OF THE INVENTION

The present invention relates to data communication techniques andintegrated circuit (IC) devices.

Over the last few decades, the use of communication networks hasexploded. In the early days of the Internet, popular applications werelimited to emails, bulletin board, and mostly informational andtext-based web page surfing, and the amount of data transferred wasrelatively small. Today, the Internet and mobile applications demand ahuge amount of bandwidth for transferring photo, video, music, and othermultimedia files. For example, a social network like Facebook processeson the order of petabytes of data daily. With such high demands on datastorage and data transfer, existing data communication systems need tobe improved to address these needs.

In high speed data communication, input buffers are often implemented inconjunction with data transmitters and digital-to-analog converters(DACs). For example, an input buffer may include an array of invertersto reduce power dissipation and improve system performance. Over thepast, there have been various techniques to implement input buffermodules. Unfortunately, they have been inadequate. Therefore, improvedcommunication systems and methods are desired.

BRIEF SUMMARY OF THE INVENTION

The present invention relates to data communication techniques andintegrated circuit devices. More specifically, embodiments of thepresent invention provide an input buffer module that utilizes one ormore equalization elements. The input buffer module includes an array ofinverters arranged in a series with an increasing drive strength with afan-out typically between 1.5 and 4. An equalization element isconfigured in series relative to a segment of the array of inverters.The resistance value of the equalization element is predetermined basedon a delay associated with the segment of the array of inverters. Thereare other embodiments as well.

According to an embodiment, the present invention provides a data inputbuffer device, which includes a first input terminal. The device alsoincludes a first plurality of inverters comprising n invertersconfigured in series, where n is two or greater. The first plurality ofinverters includes a first inverter and a first group of m inverters.The first inverter is coupled to the first input terminal. The devicealso includes a first equalization element that is characterized by apredetermined resistance value. The predetermined resistance value isbased on a delay associated with the first group of m inverters. Thefirst equalization element is configured in series relative to the firstgroup of m inverters. The device additionally includes a first outputterminal coupled to the first plurality of inverters. The device furtherincludes a second input terminal. The device additionally includes asecond plurality of inverters. The device also includes a second outputterminal coupled to the second plurality of inverters. The device alsoincludes a second equalization element coupled to the second pluralityof inverters.

According to another embodiment, the present invention provides adigital-to-analog converter (DAC) system, which includes a DAC devicebeing configured to convert n bits of input data. The system alsoincludes a first input buffer module comprising a first plurality ofinverters and a first equalization element. The first input buffermodule is configured to provide a first input signal to the DAC device.The system further includes a second input buffer module comprising asecond plurality of inverters and a second equalization element. Thesecond input buffer module is configured to provide a second inputsignal to the DAC device. The first input signal and the second inputsignal form a pair of differential inputs signals. The first pluralityof inverters includes a first a segment of m inverters. The firstsegment of m inverters is associated with a first delay value. The firstequalization element is characterized by a first predeterminedresistance value. The first predetermined resistance value is determinedbased on the first delay value.

According to yet another embodiment, the present invention provides adata input buffer device, which includes a first input terminal and afirst plurality of inverters comprising n inverters configured inseries, where n is two or greater. The first plurality of invertersincludes a first inverter and a first group of m inverters. The firstinverter is coupled to the first input terminal. The device alsoincludes a first output terminal coupled to the first plurality ofinverters. The device further includes a second input terminal. Thedevice additionally includes a second plurality of inverters comprisingn inverters configured in series. The second plurality of invertersincludes a second inverter and a second group of m inverters. The secondinverter is coupled to the second input terminal. The deviceadditionally includes a first equalization element that is characterizedby a first predetermined resistance value. The first predeterminedresistance value is based on a delay associated with the second group ofm inverters. The first equalization element is configured in seriesrelative to the second group of m inverters. The device additionallyincludes a second equalization element that characterized by a secondpredetermined resistance value, which is based on a delay associatedwith the first group of m inverters. The second equalization element isconfigured in series relative to the first group of m inverters. Thedevice also includes a second output terminal coupled to the secondplurality of inverters.

It is to be appreciated that embodiments of the present inventionprovide many advantages over conventional techniques. Among otherthings, equalization elements according to embodiments of the presentinvention lower power consumption and effectively reduce undesirableinter-symbol interference (ISI) which severely degrades the SNR, therebyeffectively improving performance of communication devices and dataprocessing devices. It is also to be finite impulse response (FIR)and/or infinite impulse response (IIR) filters cannot equalize ISIassociated with input buffer modules, and thus the equalizationtechniques according to embodiments of the present invention areuniquely effective.

Embodiments of the present invention can be implemented in conjunctionwith existing systems and processes. For example, equalization elementsutilized in input buffer modules can be readily manufactured usingexisting processes. For relatively larger devices (e.g., manufacturedusing 20 nm or larger processes), CMOS based resistors can be used toprovide resistance needed for equalization elements. For smaller devices(e.g., devices manufactured using 7 nm or 14 nm processes), smallinverter devices (ex., 1X inverters) can be configured with oppositepolarity to provide the resistance needed for equalization. Equalizationelements additionally may be used in conjunction with electricalswitches (e.g., transmission gates) to reduced unnecessary powerconsumption. It is also to be appreciated that equalization elements canflexibility be configured in many ways.

The present invention achieves these benefits and others in the contextof known technology. However, a further understanding of the nature andadvantages of the present invention may be realized by reference to thelatter portions of the specification and attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The following diagrams are merely examples, which should not undulylimit the scope of the claims herein. One of ordinary skill in the artwould recognize many other variations, modifications, and alternatives.It is also understood that the examples and embodiments described hereinare for illustrative purposes only and that various modifications orchanges in light thereof will be suggested to persons skilled in the artand are to be included within the spirit and purview of this process andscope of the appended claims.

FIG. 1 is a simplified block diagram illustrating a communication deviceaccording to embodiments of the present invention.

FIG. 2 is a simplified diagram illustrating a conventional input buffermodule.

FIG. 3 is a graph illustrating ISI associated with conventional inputbuffer module.

FIG. 4 is a simplified diagram illustrating input buffers according toembodiments of the present invention.

FIG. 5 provide graphs illustrating effect of resistor equalization forinput buffer 401.

FIG. 6 is a simplified diagram illustrating an input buffer moduleimplemented in conjunction with a DAC according to embodiments of thepresent invention.

FIG. 7 is a simplified diagram illustrating an input buffer moduleaccording to embodiments of the present invention.

FIG. 8 is a graph illustrating ISI cancellation using equalizationtechniques according to embodiments of the present invention.

FIG. 9 is a graph illustrating performance of input buffer modules withequalization resistor according to embodiment of the present invention.

FIG. 10 is a simplified block diagram illustrating an input buffermodule used for DAC applications according to embodiments of the presentinvention.

FIG. 11A is a simplified diagram illustrating an input buffer moduleimplemented with switched equalization elements according to embodimentsof the present invention.

FIG. 11B is a simplified diagram illustrating an input buffer moduleimplemented using switches as equalization elements according toembodiments of the present invention.

FIG. 12 is a simplified diagram illustrating an input buffer module withinverters as equalization elements according to embodiments of thepresent invention.

FIG. 13 is a graph illustrating performance improvement provided byequalization elements according to embodiments of the present invention.

FIG. 14 is a graph illustrating effect of equalization element accordingto embodiments of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to data communication techniques andintegrated circuit devices. More specifically, embodiments of thepresent invention provide an input buffer module that utilizes one ormore equalization elements. The input buffer module includes an array ofinverters arranged in a series. An equalization element is configured inseries relative to a segment of the array of inverters. The resistancevalue of the equalization element is predetermined based on a delayassociated with the segment of the array of inverters. There are otherembodiments as well.

As mentioned above, input buffer modules are often used in communicationdevice to receive input signals. For example, transmission (TX) inputbuffer modules are implemented in various types of data transmissiondevices. FIG. 1 is a simplified block diagram illustrating acommunication device according to embodiments of the present invention.This diagram is merely an example, which should not unduly limit thescope of the claims. One of ordinary skill in the art would recognizemany variations, alternatives, and modifications. For example, inputsignals pass through input buffer module 100 before being processed bythe main DAC as shown. Being on the data path of the input signal, inputbuffer module 100 inevitably affect signal quality.

FIG. 2 is a simplified diagram illustrating a conventional input datainput buffer module. Data are received at input terminals DATAin andDATAin bar by data input buffer module 203. A set of five inverters (4X,6X, 8X, 12X, and 20X) are configured as an input buffer array forDATAin, and through the input buffer array, data are provided to the DAC202 for processing. A similarly arranged set of five inverters areconfigured as an input buffer array for DATAin bar. For example, DATAinand DATAin bar are a pair of differential input signals. DAC 202 mayreceive n bits of input data from n slices of input buffer modules, eachprocessing a pair of data bits. For example, inverters of the input datainput buffer module 203 are implemented using CMOS inverters. Data inputbuffer module 203 can be used to drive transmitter (TX) DACs ortransmitters. For high-speed data communication applications, a largenumber of inverters may be needed to save power dissipation. Athigh-speed operation (e.g., greater than 28 GHz), CMOS based invertersoften exhibit bandwidth limitations that lead to undesirableinter-symbol interference (ISI). For example, ISI is often present atnode 201 in FIG. 2, and can degrade SNDR performance of the DAC,especially when operating in high frequency. FIG. 3 is a graphillustrating ISI associated with conventional data input buffer module.For example, after adding PRBS7 data and plotting eye diagram, effect ofISI can be shown at region 301. To minimize ISI, large inverters withrelatively high-power consumption are often needed. It is to beappreciated that embodiments of the present invention provideequalization for minimizing ISI without needing large inverters. It isto be noted that while large inverters can reduce the amount ofundesirable ISI, they cannot eliminate ISI, and they dissipateadditional power. It is thus to be appreciated equalization techniquesaccording to embodiments of the present invention can eliminate ISIwithout increasing the amount of power dissipation.

The following description is presented to enable one of ordinary skillin the art to make and use the invention and to incorporate it in thecontext of particular applications. Various modifications, as well as avariety of uses in different applications will be readily apparent tothose skilled in the art, and the general principles defined herein maybe applied to a wide range of embodiments. Thus, the present inventionis not intended to be limited to the embodiments presented, but is to beaccorded the widest scope consistent with the principles and novelfeatures disclosed herein.

In the following detailed description, numerous specific details are setforth in order to provide a more thorough understanding of the presentinvention. However, it will be apparent to one skilled in the art thatthe present invention may be practiced without necessarily being limitedto these specific details. In other instances, well-known structures anddevices are shown in block diagram form, rather than in detail, in orderto avoid obscuring the present invention.

The reader's attention is directed to all papers and documents which arefiled concurrently with this specification and which are open to publicinspection with this specification, and the contents of all such papersand documents are incorporated herein by reference. All the featuresdisclosed in this specification, (including any accompanying claims,abstract, and drawings) may be replaced by alternative features servingthe same, equivalent or similar purpose, unless expressly statedotherwise. Thus, unless expressly stated otherwise, each featuredisclosed is one example only of a generic series of equivalent orsimilar features.

Furthermore, any element in a claim that does not explicitly state“means for” performing a specified function, or “step for” performing aspecific function, is not to be interpreted as a “means” or “step”clause as specified in 35 U.S.C. Section 112, Paragraph 6. Inparticular, the use of “step of” or “act of” in the Claims herein is notintended to invoke the provisions of 35 U.S.C. 112, Paragraph 6.

Please note, if used, the labels left, right, front, back, top, bottom,forward, reverse, clockwise and counter clockwise have been used forconvenience purposes only and are not intended to imply any particularfixed direction. Instead, they are used to reflect relative locationsand/or directions between various portions of an object.

FIG. 4 is a simplified diagram illustrating data input buffer modulesaccording to embodiments of the present invention. This diagram ismerely an example, which should not unduly limit the scope of theclaims. One of ordinary skill in the art would recognize manyvariations, alternatives, and modifications. Input buffer 401 isconfigured to receive data from an input terminal DATAin as shown. Thereceived data propagate through an array of five inverters (i.e., 4X,6X, 8X, 12X, and 20X) as shown. A resistor R_(eq) is configured inparallel relative to an odd number of inverters and providesequalization. For example, resistor R_(eq) is configured in parallelrelative to inverters 6X, 8X, and 12X. Between nodes V_(x) and V_(y),the net effect of resistor R_(eq) is to provide a voltage that isopposite of the input signal received at the input terminal DATAin. Itis to be understood an odd number of inverters are configured inparallel relative to resistor R_(eq) to provide a polarity change (i.e.,between V_(x) and V_(y)) for negative cancellation signal that providesequalization. The value of resistor R_(eq) determines the equalizer tapand the number of inverters determine the amount of delay. For example,to determine the amount of resistance needed for a desired level ofequalization, the following equation is used:Vy=Rout2/Rout1+Req+Rout2DATAin−Rout1+Req/Rout1+Req+Rout2DATAin[1−DELAY]  Equation1:

As can be seen in Equation 1, the amount of equalization depends on thesize and strength of inverters. More specifically, Rout1 and Rout2correspond to equivalent resistance values of inverters. As mentionedabove, the resistance value of resistor R_(eq) is specificallycalibrated to cancel undesirable ISI in data communication. It is to benoted that ISI and consequently the resistance value of resistor R_(eq)are also based on the sample rate.

The amount of delay is based on the number of inverters configured inparallel relative to equalization resistor R_(eq). For example, inputbuffer 402 shows that inverters, configured in parallel to resistorR_(eq) effective form, a delay module. As explained above, the delaymodule for input buffer 402 includes an odd number of inverters, whichprovides the needed polarity change. The delay is determined such thatthe combination of inverters and resistor R_(eq) functions as afractionally spaced equalizer, where the delay is less than 1-unitinterval (UI). At low sample rates, the amount of delay attributed tothe inverters is substantially negligible relative to data rate, andequalization could be unnecessary. However, at high sample rate (e.g.,near 28 GHz data rate), both resistance value of R_(eq) and the amountof delay associated with inverters needs to be carefully calculated andcalibrated. For example, specific data transfer characteristics may bemeasured and used to determine the configuration (e.g., how many andwhich inverters to be used in equalization) and resistance value.

It is to be appreciated the input buffer modules illustrated in FIG. 4can be used in various applications. For example, the output of inputbuffer 401 can be coupled to DAC, NRZ driver, and/or various types oftransmitters. Depending on the implementation, input buffers 401 and 402can be configured as differential pairs or single-ended.

FIG. 5 provide graphs illustrating effect of resistor equalization forinput buffer 401. This diagram is merely an example, which should notunduly limit the scope of the claims. One of ordinary skill in the artwould recognize many variations, alternatives, and modifications. Forgiven resistance values of inverters where Rout1=400 and Rout2=200, theequalization curves corresponding to resistance values for R_(eq) at Vxnode and Vy are shown side by side. More specifically, values of R_(eq)are at infinity (i.e., open circuit or no R_(eq)), 4K, 2K, 1K, 500, and250. As can be seen from FIG. 5, as the resistance value of resistorR_(eq) decreases, the amount of equalization increases, both at Vx nodeand Vy node. It is to be appreciated that the optimal equalization valuecan be determined empirically and/or through calculation.

FIG. 6 is a simplified diagram illustrating an input buffer moduleimplemented in conjunction with a DAC according to embodiments of thepresent invention. This diagram is merely an example, which should notunduly limit the scope of the claims. One of ordinary skill in the artwould recognize many variations, alternatives, and modifications. System600 includes an n-bit DAC 602, which uses n slices of input buffermodules. For example, input buffer module 601 is one of the n inputslices. It is to be appreciated that depending on the specific bits, then slices may be configured differently. For example, least significantbits (LSB) may need fewer inverters than the most significant bits(MSB). For drive module 601, five inverters (4X, 6X, 8X, 12X, and 20X)are configured in series for DATAin input, and resistor 603 isconfigured in parallel relative to an odd (e.g., three in this specificimplementation) number of inverters: 6X, 8X, and 12X. For example,resistor 603 is specifically configured to provide the equalizationneeded by the communication system, and the three inverters in parallelto resistor 603 provide delay. A separate set of five inverters areconfigured in series for DATAin bar input, and resistor 604 isconfigured in parallel to inverters 6X, 8X, and 12X. As explained above,resistor 603 and resistor 604, configured with inverters, provideone-tap analog equalization to reduce and/or remove ISI.

FIG. 7 is a simplified diagram illustrating an input buffer moduleaccording to embodiments of the present invention. This diagram ismerely an example, which should not unduly limit the scope of theclaims. One of ordinary skill in the art would recognize manyvariations, alternatives, and modifications. FIG. 7 shows a generalizedblock diagram of an input buffer module, which can be used as inputbuffer to a DAC (as shown in FIG. 6) or other types of communicationdevices and/or components. Input signal at DATAin is coupled to inverter701. Output signal at DATAout goes out at inverter 704. Equalizationelement 702 and delay element 703 are configured in parallel. Asexplained above, equalization element 702 can be implemented using oneor more resistors, and the resistance value of equalization element 702is based on operating frequency and/or characteristics of the delayelement 702. In various embodiments, delay module 703 includes an oddnumber of inverters, which provide a predetermined amount of delay. Theresistance value of equalization element 702 depends on the sizes of theinverters at the delay element 703. Based on the implementation,resistors with fixed resistance values may be used to optimizeequalization performance under certain operating parameters. In variousembodiments, the equalization element 702 is implemented using one ormore variable resistors (e.g., implemented with CMOS transistors). Forexample, depending on the operating frequency, the resistance value ofequalization element 702 may be changed. In certain implementations,resistor may be too large to implement in to the input buffer module.For example, suitably sized resistors may be too large for 7 nmprocesses, and inverter and/or transistor may be used to implement theequalization element.

The number of inverters at the delay element 703 may depend on theimplementation of equalization element 702. Equalization element 702, ifimplemented with resistor or transistor, would require an odd number ofinverters at delay element 703 to have the polarity change. On the otherhand, if equalization element 702 is implemented using an inverter,polarity change is not needed and the delay element 703 may have an evennumber of inverters.

In various embodiments, equalization element 702 comprises a tunableresistor that is coupled to a control signal. The control signal wouldchange the resistor value based on the data sample rate and/or operatingfrequency, and the objective is to minimize and/or eliminate ISI. Forexample, by adjusting the resistance value of equalization element 702,the amount of delay can be adjusted, which in turn provides equalizationfor removing ISI.

FIG. 8 is a graph illustrating ISI cancellation using equalizationtechniques according to embodiments of the present invention. Thisdiagram is merely an example, which should not unduly limit the scope ofthe claims. One of ordinary skill in the art would recognize manyvariations, alternatives, and modifications. As can be seen at 801, ISIis virtually non-existent, wherein as there is much ISI presence shownin FIG. 3.

FIG. 9 is a graph illustrating performance of input buffer modules withequalization resistor according to embodiment of the present invention.This diagram is merely an example, which should not unduly limit thescope of the claims. One of ordinary skill in the art would recognizemany variations, alternatives, and modifications. For the purpose ofillustration, input buffer module (implemented using 16 nm technology)are configured to operate at 60 Gbps. The plot shows that the datatransmission performance of input buffer module with equalizationresistor can be much better (over 15 dB gain as measured in SNDR) thanthe input buffer module without equalization. For example, certain pulseamplitude modulation (PAM) specification requires an SNDR of at least 31dB. The input buffer module, without equalization, can drop below 30 inSNDR, which would not meet the requirement of PAM specification. It isto be appreciated that he extra margin afforded by equalization (e.g.,over 50 dB at “SS LV HT”) can be used to save power dissipation.

FIG. 10 is a simplified block diagram illustrating an input buffermodule used for DAC applications according to embodiments of the presentinvention. This diagram is merely an example, which should not undulylimit the scope of the claims. One of ordinary skill in the art wouldrecognize many variations, alternatives, and modifications. In FIG. 10,equalization resistors are cross-coupled to reduce the amount of delay(i.e., using two instead of three inverters for equalization).Equalization resistor 1002 is coupled to node 1001 and node 1003. Sincenode 1001 on the path of DATAin input and node 1003 is on the path ofDATAin bar input, the signal through resistor 1002 (originated fromDATAin at node 1003) is in opposite polarity relative to DATAin barinput after passing through two inverters, as DATAin and DATAin barinputs are in opposite polarity. Similarly, resistor 1005 is alsocross-coupled. Through cross coupling configuration, an even number ofinverters can be configured in parallel relative to the equalizationelements (e.g., resistors), which can be useful in various types ofimplementations. It is to be appreciated that other arrangements arepossible as well.

It is to be appreciated that equalization elements can be implementedusing various types of electrical components. FIG. 11A is a simplifieddiagram illustrating an input buffer module implemented with switchedequalization elements according to embodiments of the present invention.This diagram is merely an example, which should not unduly limit thescope of the claims. One of ordinary skill in the art would recognizemany variations, alternatives, and modifications. Resistor 1102 iscoupled to switch 1101, and it is configured in parallel to threeinverters on the “DATAin” data path as shown. Similarly, resistor 1104is coupled to switch 1103, and it configured in parallel to threeinverters on the “DATAin bar” data path. For example, switches 1101 and1103 can be implemented using transmission gates as shown, but it is tobe understood that other types of switches can be used as well. Forexample, switches 1101 and 1103 are coupled to a control module (notshown), which sends control signal to enable or disable resistors 1102and 1104. For example, when there is no data transmission on thecommunication lanes (e.g., power down or loss of signal), resistor 1102and resistor 1104 are disable to eliminate unnecessary powerdissipation. It is to be noted that switch 1101 and switch 1103 arecharacterized by their own resistance values. And thus, the resistancesof equalization elements are dictated by both R_(OR) and R_(Poly) (e.g.,resistance of polysilicon based resistor). For example, the resistancevalue R_(OR) of switch 1101 at the “on” state is used when determiningthe needed resistance value of resistor 1102.

The required resistance value of the equalization element may besufficiently small that the resistance of the switches would besufficient. FIG. 11B is a simplified diagram illustrating an inputbuffer module implemented using switches as equalization elementsaccording to embodiments of the present invention. This diagram ismerely an example, which should not unduly limit the scope of theclaims. One of ordinary skill in the art would recognize manyvariations, alternatives, and modifications. As shown in FIG. 11B,equalization elements are implemented using switch 1105 and switch 1106as shown. For example, switch 1105 is implemented using a transmissiongate, and it is configured in parallel relative to three inverters(i.e., 6X, 8X, 12X) on the “DATAin” signal path. The switch 1105 acts asboth a switch and a resistor. For example, when there is no signal onthe data path “DATAin”, switch 1105 receives a control signal (e.g.,from a control module) that turns switch 1105 off to save power. Whenswitch 1105 is on, the resistance of switch 1105 (e.g., implementedusing a transmission gate) is used for equalization. In variousimplementations, for devices manufactured using 7 nm processes, aresistor (e.g., a polysilicon implementation of resistor) may occupy toomuch area, and the resistance afforded by switch 1105 may suffice.Switch 1106 similar functions both as a switch and an equalizationelement.

FIG. 12 is a simplified diagram illustrating an input buffer module withinverters as equalization elements according to embodiments of thepresent invention. This diagram is merely an example, which should notunduly limit the scope of the claims. One of ordinary skill in the artwould recognize many variations, alternatives, and modifications. Asexplained above, resistors (e.g., polysilicon based resistors) may betoo large for small devices (e.g., devices manufactured using 7 nmprocesses). In various embodiments, small inverters are used asresistors to provide equalization. Inverters 1201 and 1202 areconfigured to function as equalization elements with their outputshaving opposite polarity from the data signals. Even small inverters canhave large impedance values, and thus relative small inverters are usedto function as resistors for equalization. As shown in FIG. 12, inverter1201 is a small “1X” inverter that is configured in parallel to largeinverters (e.g., 4X, 8X, and 16X) as shown.

FIG. 13 is a graph illustrating performance improvement provided byequalization elements according to embodiments of the present invention.For example, equalization elements are implemented in PAM4 communicationsystems with circuits manufactured using 7 nm processes. Curve 1301shows SNDR (measured in dB) of an input buffer module withoutequalization elements. Curve 1302 shows SNDR of an input buffer modulethat uses a transmission gate for equalization (e.g., illustrated inFIG. 11B), which provides a sizable improvement (almost 15 dB gain at“SS lowV Hot”). Curve 1303 shows SNDR of an input buffer module thatuses inverter for equalization (e.g., illustrated in FIG. 12), and ithas a large improvement over curve 1301. Curve 1304 and curve 1305 showSNDRs of input buffer modules that use resistors (e.g., differentresistor implementations) for equalization, which provides largeperformance gain over input buffer module without equalization.

FIG. 14 is a graph illustrating effect of equalization element accordingto embodiments of the present invention. This diagram is merely anexample, which should not unduly limit the scope of the claims. One ofordinary skill in the art would recognize many variations, alternatives,and modifications. For example, the measurement of effective number ofbits (ENOB) on the y-axis is associated with a 7-bit DAC operating at 60GS/s (at an output frequency of about 27 GHz). As shown in FIG. 14, theshaded area 1401 is a sweet spot where ENOB measurements are highest,and the corresponding resistance values (in ohms) are shown. For thisparticular system, resistance value is around 2000 ohms. It is to beunderstood that depending on the specification implementation, optimalresistance value of the equalization element may vary. For example,optimal resistance value for equalization can be determined empiricallyand/or through calculation.

While the above is a full description of the specific embodiments,various modifications, alternative constructions and equivalents may beused. Therefore, the above description and illustrations should not betaken as limiting the scope of the present invention which is defined bythe appended claims.

What is claimed is:
 1. An input buffer device comprising: a first inputterminal; a first input slice including a first plurality of invertersthat comprises n inverters configured in series, n indicating a firstquantity of inverters and being two or greater, the first plurality ofinverters including a first inverter and a first group of m inverters, mindicating a second quantity of inverters, the first inverter beingcoupled to the first input terminal; and a first equalization elementcharacterized by a predetermined resistance value, the predeterminedresistance value being based on a delay associated with the first groupof m inverters, the first equalization element being configured inseries relative to the first group of m inverters.
 2. The device ofclaim 1 wherein the first equalization element comprises a resistor. 3.The device of claim 1 wherein the first equalization element comprises aresistor and a switch.
 4. The device of claim 3 wherein the switchdisables the first equalization element if a control signal indicates nosignals on the first input terminal.
 5. The device of claim 1 wherein mis an odd integer.
 6. The device of claim 1 wherein the firstequalization element comprises an inverter.
 7. The device of claim 1wherein the resistance value is between 500 ohms and 5000 ohms.
 8. Thedevice of claim 1 wherein the first input terminal and the second inputterminal receive differential input signals.
 9. The device of claim 1further comprising: a first output terminal coupled to the firstplurality of inverters; a second input terminal; a second plurality ofinverters; a second output terminal coupled to the second plurality ofinverters; and a second equalization element coupled to the secondplurality of inverters.
 10. The device of claim 1 further comprising asecond input slice comprising a second plurality of inverters, thesecond plurality of inverters comprising k number of inverters, k beingless than n.
 11. The device of claim 10 wherein the first input slicecorresponds to an MSB and the second input slice corresponds to an LSB.12. A circuit device comprising: a DAC device configured to convert nbits of input data, n indicating a number of bits; a first input buffermodule comprising a first plurality of inverters and a firstequalization element, the first input buffer module being configured toprovide a first input signal to the DAC device, the first plurality ofinverters includes a first a segment of m inverters, m indicating aquantity of inverters, the first segment of m inverters being associatedwith a first delay value, the first equalization element beingcharacterized by a first predetermined resistance value, the firstpredetermined resistance value being determined based on the first delayvalue; and a pre-distortion array coupled to the first input buffermodule.
 13. The system of claim 12 further comprising a second inputbuffer module comprising a second plurality of inverters and a secondequalization element, the second input buffer module being configured toprovide a second input signal to the DAC device, wherein the first inputsignal and the second input signal form a pair of differential inputssignals.
 14. The system of claim 12 wherein each of the n input buffermodules provides a pair of differential input signals.
 15. The system ofclaim 12 wherein m is an odd integer.
 16. The system of claim 12 whereinthe first equalization element comprises a resistor.
 17. The system ofclaim 12 wherein the first equalization element comprises a transmissiongate and a resistor.
 18. The system of claim 13 wherein: the secondplurality of inverters includes a second a segment of m inverters, thesecond segment of m inverters being associated with a second delayvalue; and the second equalization element is characterized by a secondpredetermined resistance value, the second predetermined resistancevalue being determined based on the second delay value.
 19. A data inputbuffer device comprising: a first input terminal; a first plurality ofinverters comprising n inverters configured in series, n indicating afirst quantity of inverters and being two or greater, the firstplurality of inverters including a first inverter and a first group of minverters, m indicating a second quantity of inverters, the firstinverter being coupled to the first input terminal; a first outputterminal coupled to the first plurality of inverters; a second inputterminal; a second plurality of inverters comprising n invertersconfigured in series, the second plurality of inverters including asecond inverter and a second group of m inverters, the second inverterbeing coupled to the second input terminal; a first equalization elementbeing characterized by a first predetermined resistance value, the firstpredetermined resistance value being based on a delay associated withthe second group of m inverters, the first equalization element beingconfigured in series relative to the second group of m inverters; aswitch coupled to the first equalization element; and a second outputterminal coupled to the second plurality of inverters.
 20. The device ofclaim 19 further comprising a second equalization element beingcharacterized by a second predetermined resistance value, the firstpredetermined resistance value being based on a delay associated withthe first group of m inverters, the second equalization element beingconfigured in series relative to the first group of m inverters.